A High(er) Power H-Bridge for Servo control - Initial Tests

by Ivan Hamilton 9/6/2011 7:58:00 PM

So, with my prototype assembled, it was time for some basic signal tests. The first thing that became obvious, is that my CRO is quite dusty - but I think it adds character. Anyway, on with it...


Lower trace (2V/5µS/div): 3.3V input @ 25Khz ~50% duty.
Upper trace (2V/5µS/div): 5V output of the opto-isolator.

As mentioned previously, the output from the opto-isolator is inverted from the input signal. It's also clear that the switch on/off characterists aren't the same. The 5V signal falls in ~1µS, but takes ~3µS to rise. Passing this thru digital logic chips may help square up the transitions.


Lower trace (2V/5µS/div): 3.3V input @ 25Khz 50% duty.
Upper trace (2V/5µS/div): 5V output of the inverter (NAND gate).

After passing thru the inverter (NAND gate), the edges certainly are squarer. The slowness of the low-high transition at the opto-isolator (~3µS) has resulted in a noticable (~0.5µS) slope on the high-low transition out of the 4011 NAND gate. I really don't think this is a problem, but could be addressed by using a 4093 (Schmitt Triggered) version of the NAND chip (a whopping $0.02 extra per chip).


Lower trace (2V/5µS/div): 3.3V input @ 25Khz 50% duty.
Upper trace (5V/5µS/div): gate drive to the lower mosfet.

The gate drive to the lower mosfet. As soon as the 3.3V input goes high, the lower mosfet is switched off. But when the 3.3V input goes low, there is a slight delay before switching on - to allow the upper mosfet time to fully switch off(deadtime),


Lower trace (2V/5µS/div): 3.3V input @ 25Khz 50% duty.
Upper trace (5V/5µS/div): gate drive to the upper mosfet.

The gate drive to the upper mosfet. As soon as the 3.3V input goes low, the upper mosfet is switched off. But when the 3.3V input goes high, there is a slight delay before switching on - to allow the lower mosfet time to fully switch off(deadtime).


Lower trace (5V/5µS/div): gate drive to the lower mosfet.
Upper trace (5V/5µS/div): gate drive to the upper mosfet.

The gate drive to both upper and lower mosfets. Remember, the duty cycle wasn't setup at exactly 50%.


Dual traces (5V/5µS/div): gate drive to the upper & lower mosfets overlaid.

The dead time is blatantly obvious here. You can see the ~1µS delay between switch off of one mosfet & switch on of the other. I've heard that 500nS should be plenty, and this could easily be adjusted by changing the deadtime resistor connected to the IR21884. 


Dual traces (5V/5µS/div): gate drive to the upper & lower mosfets overlaid with 10V motor & supply connected.

Up until this point, I hadn't supplied any voltage on the motor supply terminals. Therefore (referenced to ground), the voltage on the upper gates was simply the gate supply (12V). To turn on N-channel mosfets you must provide a positive voltage at the gate relative to the source. For a high-side mosfet, where the mosfet source is intended to supply the motor at full motor voltage, this means the gate voltage must be above the motor supply voltage.

The taller of the two pulses is the high-side gate (the smaller, the low-side gate). With 12V for gate supply, and 10V motor supply, you can see the boot-strap circuitry is producing a ~20V (relative to ground) gate voltage for the high side, and ~12V for low side.

I'm not sure about the ringing that's visible. It may be coming from the motor that was connected at the time, or it could have been EM picked up by the probes - I'm not really sure.


Dual traces (5V/2µS/div): Zoom of gate drive to the upper & lower mosfets overlaid with 10V motor & supply connected.

That's just the ringing a bit closer up...  


Lower trace (50mV/5µS/div): Current sense input.
Upper trace (5V/5µS/div): gate drive to the upper mosfet.

Here's the gate drive voltage & current sense resistor voltage. You can see how after turn on, the voltage across the sense resistor rises as the motor's inductance allows current to increase.

It also shows the reverse (negative) current cased by back EMF flowing thru the sense resistor after turn-off (0V is actual the "0%" horizontal line on the bottom trace).


Lower trace (2V/5µS/div): output of current sense latch
Upper trace (50mV/5µS/div): Current sense input.

Catching the comparator's output on my analog scope provded quite tricky (maybe I need a new DSO), because as soon as the comparator switched on, the mosfets switch off and the comparator switched off again.

So this is the current sense & output from the latch (being reset by the comparator). The current reference was set to 50mV which thru a single 20mΩ current sense resistor is 2.5A. 0V on the top trace is the 4th horizontal line from the top.

When the current sense voltage reached 50mV, the enable line to the mosfet drivers was shut-off (which stopped further current increases). The enable line would then by set high again by the next rise in the A or B inputs.


Lower trace (2V/10µS/div): output of current sense latch
Upper trace (5V/10µS/div): high mosfet gate drive.

Here's a perfect shot the current limiting in action. During the first cycle the gate switches on and off as commanded. During the second cycle, the current limit is exceeded resulting in the enable line being sent low (switching off the mosfet). The 3rd cycle (left most side - we can only see the start of it) sets the enable line high again, and switches the mosfet on again.

It's all appears to be functioning as designed... Yippee! But if I did this for a living (especially documenting it)... a nice big 4 channel DSO would be in order.

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